NXP Semiconductors /LPC15xx /USART0 /CFG

USART Enable.

0 (DISABLED): Disabled. The USART is disabled and the internal state machine and counters are reset. While Enable = 0, all USART interrupts and DMA transfers are disabled. When Enable is set again, CFG and most other control bits remain unchanged. For instance, when re-enabled, the USART will immediately generate a TxRdy interrupt (if enabled in the INTENSET register) or a DMA transfer request because the transmitter has been reset and is therefore available.

1 (ENABLED): Enabled. The USART is enabled for operation.

Reserved. Read value is undefined, only zero should be written.

Selects the data size for the USART.

0 (7_BIT_DATA_LENGTH): 7 bit Data length.

1 (8_BIT_DATA_LENGTH): 8 bit Data length.

2 (9_BIT_DATA_LENGTH): 9 bit data length. The 9th bit is commonly used for addressing in multidrop mode. See the ADDRDET bit in the CTL register.

3 (RESERVED): Reserved.

Selects what type of parity is used by the USART.

0 (NO_PARITY): No parity.

1 (RESERVED): Reserved.

2 (EVEN_PARITY): Even parity. Adds a bit to each character such that the number of 1s in a transmitted character is even, and the number of 1s in a received character is expected to be even.

3 (ODD_PARITY): Odd parity. Adds a bit to each character such that the number of 1s in a transmitted character is odd, and the number of 1s in a received character is expected to be odd.

Number of stop bits appended to transmitted data. Only a single stop bit is required for received data.

0 (1_STOP_BIT): 1 stop bit.

1 (2_STOP_BITS): 2 stop bits. This setting should only be used for asynchronous communication.

Reserved. Only write 0 to this bit.

Selects standard or 32 kHz clocking mode.

0 (UART_USES_STANDARD_C): UART uses standard clocking.

1 (UART_USES_THE_32_KHZ): UART uses the 32 kHz clock from the RTC oscillator as the clock source to the BRG, and uses a special bit clocking scheme.

Reserved. Read value is undefined, only zero should be written.

CTS Enable. Determines whether CTS is used for flow control. CTS can be from the input pin, or from the USART’s own RTS if loopback mode is enabled. See Section 24.7.4 for more information.

0 (NO_FLOW_CONTROL): No flow control. The transmitter does not receive any automatic flow control signal.

1 (FLOW_CONTROL_ENABLED): Flow control enabled. The transmitter uses the CTS input (or RTS output in loopback mode) for flow control purposes.

Reserved. Read value is undefined, only zero should be written.

Selects synchronous or asynchronous operation.

0 (ASYNCHRONOUS_MODE_IS): Asynchronous mode is selected.

1 (SYNCHRONOUS_MODE_IS): Synchronous mode is selected.

Selects the clock polarity and sampling edge of received data in synchronous mode.

0 (FALLING_EDGE): Falling edge. Un_RXD is sampled on the falling edge of SCLK.

1 (RISING_EDGE): Rising edge. Un_RXD is sampled on the rising edge of SCLK.

Reserved. Read value is undefined, only zero should be written.

Synchronous mode Master select.

0 (SLAVE): Slave. When synchronous mode is enabled, the USART is a slave.

1 (MASTER): Master. When synchronous mode is enabled, the USART is a master.

Selects data loopback mode.

0 (NORMAL_OPERATION): Normal operation.

1 (LOOPBACK_MODE): Loopback mode. This provides a mechanism to perform diagnostic loopback testing for USART data. Serial data from the transmitter (Un_TXD) is connected internally to serial input of the receive (Un_RXD). Un_TXD and Un_RTS activity will also appear on external pins if these functions are configured to appear on device pins. The receiver RTS signal is also looped back to CTS and performs flow control if enabled by CTSEN.

Reserved. Read value is undefined, only zero should be written.

Output Enable Turnaround time enable for RS-485 operation.

0 (DISABLED): Disabled. If selected by OESEL, the Output Enable signal deasserted at the end of the last stop bit of a transmission.

1 (ENABLED): Enabled. If selected by OESEL, the Output Enable signal remains asserted for one character time after the end of the last stop bit of a transmission. OE will also remain asserted if another transmit begins before it is deasserted.

Automatic Address matching enable.

0 (DISABLED): Disabled. When addressing is enabled by ADDRDET, address matching is done by software. This provides the possibility of versatile addressing (e.g. respond to more than one address).

1 (ENABLED): Enabled. When addressing is enabled by ADDRDET, address matching is done by hardware, using the value in the ADDR register as the address to match.

Output Enable Select.

0 (STANDARD): Standard. The RTS signal is used as the standard flow control function.

1 (RS_485): RS-485. The RTS signal configured to provide an output enable signal to control an RS-485 transceiver.

Output Enable Polarity.

0 (LOW): Low. If selected by OESEL, the output enable is active low.

1 (HIGH): High. If selected by OESEL, the output enable is active high.

Receive data polarity.

0 (STANDARD): Standard. The RX signal is used as it arrives from the pin. This means that the RX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.

1 (INVERTED): Inverted. The RX signal is inverted before being used by the UART. This means that the RX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.

Transmit data polarity.

0 (STANDARD): Standard. The TX signal is sent out without change. This means that the TX rest value is 1, start bit is 0, data is not inverted, and the stop bit is 1.

1 (INVERTED): Inverted. The TX signal is inverted by the UART before being sent out. This means that the TX rest value is 0, start bit is 1, data is inverted, and the stop bit is 0.

Reserved. Read value is undefined, only zero should be written.